1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a method of forming a wiring layer and an electrode of a MOS semiconductor device using a selfaligned silicidation technique.
2. Description of the Related Art
FIGS. 1A to 1C collectively show a method of directly achieving an ohmic contact between source or drain diffusion layers and a polysilicon film used as a wiring layer. These drawings show a p-type silicon substrate 1, an insulation film 2 for separating elements, i.e., for separating adjacent MOS transistors from each other, a gate insulation film 3, polysilicon films 4a, 4b, a gate electrode 4c formed of a polysilicon film, a wiring 4d formed of a polysilicon, n-type source/drain regions 5a/5b, and a diffusion layer 5c for an n-type contact.
To be more specific, the polysilicon film 4a is deposited on the insulation film 2 for element separation, which is formed on the surface of the substrate 1, and on the gate insulation film 3 in an active element region surrounded by the insulation film 2, as shown in FIG. 1A. Then, the polysilicon film 4a and the gate insulation film 3 are selectively removed by the lithography technique so as to form an opening 6. Further, the polysilicon film 4b is deposited on the entire surface, with the result that the polysilicon film 4b is in direct contact with the substrate 1 via the opening 6, as shown in FIG. 1B.
In the next step, an impurity is introduced into the polysilicon film 4b so as to lower the resistance of the polysilicon film 4b and to achieve an ohmic contact between the substrate 1 and the polysilicon film 4b. Then, the polysilicon film 4b is patterned by the lithography technique so as to form the polysilicon gate electrode 4c and a direct contact region between the polysilicon wiring 4d and the source region 5a. Thereafter, a MOS transistor provided with the gate electrode 4c is formed by the ordinary method.
In the conventional technique described above, however, it is impossible to remove completely a natural oxide film within the opening 6 for forming a contact region. It follows that the natural oxide film remains at the interface between the polysilicon film 4b and the substrate 1, leading to a high contact resistance.
It should also be noted that the impurity is introduced into the polysilicon film 4b by means of an ion implantation technique or a gaseous phase diffusion technique in order to achieve an ohmic contact between the polysilicon film 4b and the substrate 1. For achieving the ohmic contact, i.e., for sufficiently reducing the contact resistance, an impurity should be introduced with a high concentration. As a result, the junction depth of the diffusion layer 5c in the contact region formed in the substrate 1 is made deeper than that of the diffusion layer 5a. It follows that the withstand voltage is lowered between the diffusion layers of the adjacent active regions separated from each other by the element separating insulation film 2, i.e., between the diffusion layer 5c shown in FIG. 1C and the diffusion layer corresponding to the diffusion layer 5a of the adjacent active region (not shown). What should be noted is that, in the prior art shown in FIG. 1C, the improvement in the contact resistance bring about a low withstand voltage, and vice versa.